In response to the recent advancement in electronic devices achieving improved functionality and performance, semiconductor integrated circuits mounted in such electronic devices have an increased complexity of integration (the number of semiconductor elements integrated on one chip) and an increased chip size. In order to avoid such increase in chip size, there is a need for micro-fabrication (reduction in design rule) of the semiconductor integrated circuits.
A semiconductor integrated circuit chip can be divided into two major regions: an operational region (also known as an active region) inside the chip; and a bonding pad region on a chip surface. The operational region includes a region (active region) where semiconductor elements such as transistors are formed, and a metal wiring region (wiring region) that connects the semiconductor elements together. The bonding pad region is a region where a bonding pad is formed. The bonding pad is an electrode for making electrical connections with outside, for example, by wire bonding using thin gold leads, so that signals can be sent in and out of the semiconductor integrated circuit.
As the semiconductor elements become denser and more highly integrated, the metal pattern connecting these elements has become complex, and it is now common practice to employ a multi-layer wiring structure in which a plurality of wiring layers are laminated via interlayer insulating films. As a result, a liquid crystal driver LSI, for example, now has 500 to 1000 terminals for making connections with external terminals. This has increased the area of the bonding pad other than the operational region (active region), and brought a proportional increase in the size of the semiconductor integrated circuit. This is a setback in realizing lighter, thinner, and smaller electronic devices, such as cellular phones and PDA (Personal Digital Assistant).
One conventional method of reducing the chip size is to form the bonding pad in an active region of a semiconductor substrate. This method is known as the “area pad” method. The following describes conventional techniques concerning the area pad method.
FIG. 26 illustrates one example of the area pad method for a semiconductor device of a bi-layer wiring structure, disclosed in Japanese Publication for Unexamined Patent Application No. 2002-198374 (Tokukai 2002-198374; Published on Jul. 12, 2002). In the semiconductor device shown in FIG. 26, a first wiring layer 2 is connected to an active region of a silicon substrate 1, a second wiring layer 7 is formed on the first wiring layer 2 via an interlayer insulating film 6, and a bonding pad 14 is disposed over the second wiring layer 7 via a protective film 8 and a polyimide film 10, covering the active region of the silicon substrate 1.
In an area covered with the bonding pad 14, the second wiring layer 7 has a plurality of wires 7a and 7b. The bonding pad 14 is bonded to a wire 7a of the second wiring layer 7 through openings 9 and 11 of the protective film 8 and the polyimide film 10. Between the bonding pad 14 and the wires 7b are interposed the protective film 8 and the polyimide film 10.
With the semiconductor device of the foregoing structure, the fabrication steps can be simplified and the size of the device can be reduced at the same time. In addition, the foregoing structure offers more flexibility in terms of positioning of the bonding pad and wire connections between the bonding pad and the semiconductor elements.
Referring to FIG. 26 through FIG. 34, a fabrication process of the semiconductor device is described below. First, as shown in FIG. 27, an element 20, such as a MOS (Metal Oxide Semiconductor) transistor, is formed on a main surface (simply “surface” hereinafter) of the silicon (Si) substrate 1 according to common fabrication procedures of semiconductor integrated circuits.
Then, using a CVD (Chemical Vapor Deposition) method, an insulating film 25 is deposited to a predetermined thickness over the entire surface of the silicon substrate 1. As a result, the insulating film 25 covers the active region. Thereafter, contact holes are formed through predetermined positions of the insulating film 25. The contact holes are formed according to common fabrication steps of a semiconductor integrated circuit, including, for example, a photolithography step, and an etching step for the insulating film.
Next, the first wiring layer 2, which is a first layer of wiring, is deposited over the entire surface, including the insulating film 25 and the openings. The first wiring layer 2 may be a single-layer metal thin film, or a laminate of metal. Alternatively, the first wiring film 2 may be a laminate of a semiconductor thin film and metal, wherein a material with a small resistivity is used for the laminate. In this conventional technique, a laminate of a TiW thin film of about 310 nm thick and an AlSi thin film of about 600 nm thick is used. The first wiring layer 2 is then processed into a predetermined shape to form wires 2a and 2b, which make up the first layer of wiring. As a result, wiring is made between each element and electrodes and between the elements as well.
Thereafter, as shown in FIG. 28, the first interlayer insulating film 6 is formed over the entire surface, including the first wiring layer 2. The first interlayer insulating layer 6 may be a single-layer insulating film, or more preferably a laminate of multiple insulating films to planarize irregularities of the wirings 2a and 2b making up the first wiring layer 2. In this conventional technique, the first interlayer insulating film 6 is formed by the following sequence of steps. First, a SiOx film 3 of about 500 nm thick is formed over the entire surface, including the first wiring layer 2, using a plasma CVD method. Then, an SOG (Spin on Glass) film 4 is formed in recessed portions of the SiOx film 3, using an SOG film/etch back process. Finally, a SiOx film 5 of about 450 nm thick is formed over the SiOx film 3 and the SOG film 4, using a CVD method.
The SOG film 4, also known as a coated silicon oxide film, is a silicon oxide film formed by a coating method (SOG). The SOG film 4 is highly effective to achieve planarization because it can be formed by simple spin coating (coating method), and because it forms in recessed portions, rather than raised portions, of the coated surface due to the surface tension. However, using the SOG film 4 alone as the first interlayer insulating film 6 is not preferable because a trace amount of water or other components contained in the SOG film 4 seeps out and reacts with the material of the metal wiring, causing a problem of disconnected wires in the metal wiring.
In order to avoid such a problem, the entire surface of the SOG film 4 is etched by a technique known as an etch back process after forming the SOG film over the entire surface of the SiOx film 3. As a result, the SOG film 4 remains only in the recessed portions of the SiOx film 3, planarizing the surface. Then, the SiOx film 5 is formed over the planarized surface by a CVD method. In this manner, the SOG film 4 is sandwiched between the SiOx film 3 and the SiOx film 5, thereby preventing water or other components from seeping out of the SOG film 4.
Thereafter, as shown in FIG. 29, an opening (via hole) 6a is formed through a predetermined portion of the first interlayer insulating film 6. One function of the opening 6a is to connect the wires of the first wiring layer 2 to one another. The opening 6a is formed by first etching the insulating film isotropically to provide a predetermined slant at a stepped portion, followed by anisotropic etching of the insulating film.
Thereafter, as shown in FIG. 30, the second wiring layer 7 is formed by depositing a conductive material on the first interlayer insulating film 6 and in the opening 6a. The second wiring layer 7 is then patterned into a predetermined wiring pattern to form second wires 7a through 7c. In this conventional technique, the second wiring layer 7 is a laminate of a TiW film of about 150 nm thick and an AlSi film of about 1100 nm thick, for example.
Then, as shown in FIG. 31, the protective film 8 is formed over the second wiring layer 7. The protective film 8 is provided to protect the surface of the semiconductor integrated circuit, and to insulate an area pad of an Au bump from the second wires 7a through 7c of the second wiring layer 7. As the protective film 8, a laminate of a SiOx film and a SiN film, both of which are formed by a plasma CVD method, is used.
Thereafter, as shown in FIG. 32, an opening 9 is formed at a predetermined position of the protective film 8. The opening 9 is provided to provide external electrical connections for the first wires 2a and 2b and the second wires 7a and 7b. 
Next, as shown in FIG. 33, the polyimide film 10 is applied and deposited on the protective film 8 and in the opening 9. The polyimide film 10 is provided as a film (shock absorber film) for absorbing the stress generated when the chip formed with the area pad is bonded to the substrate.
Thereafter, as shown in FIG. 34, an opening 11 is formed at a predetermined position of the polyimide film 10. The opening 11 is formed in such a manner that only the wire 7a is exposed among the plurality of wires 7a and 7b of the second wiring layer 7 covered with the protective film 8. Here, the inner wall of the opening 11 is slanted in the form of a bird's beak by isotropic etching, as shown in FIG. 34.
The opening is positioned and sized such that the opening includes and is larger than the area of the opening through the protective film, and that the opening is sufficiently smaller than the size of the Au bump 13, i.e., the size of the area pad, formed above. In the area pad of the conventional technique, the opening measures about 10 μm×10 μm, because the shock absorber is required above the second wires 7a and 7b of the second wiring layer 7 beneath the area pad.
Then, as shown in FIG. 26, the bonding pad 14, including the barrier metal 12 and the Au bump 13, is formed over the openings 9 and 17 of the protective film 8 and the insulating film 15, and over the plurality of wires 7a and 7b of the second wiring layer 7 covered with the protective film 8.
More specifically, first, a thin film of metal and a thin film of gold (Au), which together make up the barrier metal 12, are deposited. The barrier metal 12 is provided to prevent a chief metal of the area pad, for example, such as gold (Au), from reacting with the material of the conductive layer constituting the wires. The barrier metal 12 also serves as an electrode when forming the area pad by plating.
Thereafter, using the barrier metal 12 as an electrode, the Au bump 13, having a predetermined thickness, is formed in a predetermined position, i.e., the area pad is formed. The Au bump 13 is sized to have larger dimensions than the opening 11 through the polyimide film 10. Then, using the Au bump 13 as a mask, unnecessary portions of the barrier metal 12 are removed to form the bonding pad 14.
In the conventional technique, the barrier metal 12 is formed by depositing a TiW thin film of 250 nm thick and a Au thin film of 170 nm thick. Then, using the thin film of the barrier metal 12 as an electrode, gold (Au) is plated to a thickness of about 10 μm, thereby forming a Au bump 13 (area pad) that measures approximately 35 μm×50 μm.
In the semiconductor device of a bi-layer wiring structure disclosed in the foregoing publication Tokukai 2002-198374, at least two steps are required to form the polyimide film 10: a step of applying and depositing polyimide in a portion where the bonding pad 14 is to be formed; and a step of forming an opening through a predetermined portion of the polyimide film 10 to provide the opening 11. As a result, additional steps of photolithography and etching are required, resulting in poor working efficiency and increased chip cost.
Omitting the polyimide film 10 to avoid this problem may damage the structural elements underneath the bonding pad 14 by the stress exerted during mounting such as COF (Chip on Film), because in this case no shock absorber is provided.
The foregoing publication Tokukai 2002-198374 also discloses a structure in which the protective film 8 has overhung protrusions, as shown in FIG. 35 and FIG. 36, so that the interface of the protective film 8 and the polyimide film 19 has improved adhesion. As the term is used herein, “overhung” is an upper portion of the protective film 8 extending outward from the base portion. Specifically, as illustrated in FIG. 36, the overhung portion is a portion defined by X>Y, where X is the maximum outer dimension of a protrusion 8b along a direction parallel to the substrate surface (direction orthogonal to the wire 7b in the example of FIG. 36), and Y is a dimension of the lowest portion of the protrusion 8b along this direction.
This enables the polyimide film 10 to be deposited also on pinched portions 8a of the overhung protrusion 8b, allowing the protrusions 8b of the protective film 8 to hook the polyimide film 10 at the pinched portions 8a. As a result, the protective film 8 and the polyimide film 10 can have improved adhesion.
However, owning to the fact that the thickness of the overhung protrusion 8b is thin at the pinched portions 8a, a crack 27 was observed at a plurality of pinched portions 8a of the protective film 8, as shown in FIG. 36 and FIG. 37, when stress was applied during mounting such as COF after forming the Au bump 13 in the semiconductor integrated circuit.
Here, water may seep into a circuit structure, such as the second wire 7b, through the crack 27. In this case, if current flows into the portion soaked with water, the metal wiring is corroded, leading to disconnection of the wires over time.